Pipelining in Computer Architecture

Pipelining

Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows for storing and executing instructions in an orderly process. It also known as pipeline processing. Pipelining is a technique where multiple instructions overlapped during execution. It divided into stages and these stages connected to form a pipe-like structure. Instructions enter from one end and exit from another end.

Pipelining will increase the performance of the CPU meaning executing more instructions in less time. In a pipeline system, each segment consists of an input register followed by a combinational circuit. The register used to hold data and a combinational circuit performs operations on it. The output of the combinational circuit is applied to the input register of the next segment. The pipeline system is like the modern-day assembly line set up in factories.

Example: In a car manufacturing industry, huge assembly lines are set up and at each point, there are robotic arms to perform a certain task, and then the car moves on ahead to the next arm.

Types of pipelining

The pipeline is mainly divided into 2 categories:

• Arithmetic Pipeline
• Instruction Pipeline

Arithmetic Pipeline

Arithmetic pipelines usually found in most computers. These pipelines are used to divide an arithmetic task into subtasks to be executed in different pipeline segments. They are used for floating point operations, multiplication of fixed point numbers etc.

Instruction Pipeline

An Instruction pipeline reads instructions from the memory while previous instructions are executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segments of equal duration.

It is similar to the use of an assembly line in a manufacturing plant. In an assembly line, the product goes through various stages of production. The advantage of such a system is that products at various stages can be worked on simultaneously. This process is known as pipelining since just like a pipeline, new inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.

We can consider the instruction processing to consist of two stages: fetch the instruction and execute the instruction. There are times during the execution of an instruction when the main memory is not being accessed. This time could be used to fetch the next instruction in parallel with the execution of the current one.

The above figure shows depict this where the pipeline has two independent stages. The first stage fetches an instruction and buffers it. When the second stage is free, the first stage passes the buffered instruction. While the second stage is executing the instruction, the first stage fetches and buffers the next instruction. This is called instruction prefetch or fetch overlap.

In general, pipelining requires more registers to store data between the stages. The above figure shows an expanded view of this concept. To speed up the instruction cycle processing, the pipeline should have more stages.

Pipelining Hazards

In a pipelined design, few instructions are in some stage of execution. There are possibilities for some dependency amongst these sets of instructions and thereby limiting the speed of the Pipeline. The dependencies occur for a few reasons. Those dependencies in this pipeline called Hazards. There are mainly three different types of hazards in computer architecture are:

1. Structural Hazards: Hardware resource conflicts among the instructions in the pipeline cause structural hazards. When more than one instruction in the pipe requires access to the very same resource in the same clock cycle, a resource conflict said to Structural Hazard.

2. Data Hazards: When several instructions are in partial execution, and if they reference the same data then the problem arises. We must ensure that the next instruction does not attempt to access data before the current instruction because this will lead to incorrect results.

3. Control Hazards: To fetch and execute the next instruction, we must know what that instruction is. If the present instruction is a conditional branch, its result will lead us to the next instruction, then the next instruction may not be known until the current one is processed.