Cache Memory Mapping Techniques
The clock speed of the CPU is much faster than the main memory, So, the CPU requires a fast memory. Such a fast and small memory is referred to as a ‘cache memory‘. The Cache Memory is the intermediate Memory between CPU and main memory.
Basic Operation of Cache Memory:
When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is read from cache memory. If the word isn’t found in the cache, the CPU read the word from the main memory and the same word copied into cache memory from main memory.
Cache Hit Ratio:
The performance of cache memory is measured in terms of a quantity called “Hit Ratio“. If the word isn’t found in the cache memory, it is in main memory, it counts as ‘miss‘, if the word is found in the cache memory then it is called ‘hit‘. The ratio of the number of hits divided by the total CPU references to memory (hit+misses) is the hit ratio.
The basic characteristics of cache memory are its fast access time. So, it is very little or no time must be wasted when searching for words in the cache. The transformation of data from main memory to cache memory is referred to as a ‘Mapping‘ process. There are 3 types of mapping procedure are there for cache memory:
1. Associative Mapping
2. Direct Mapping
3. Set-Associative Mapping
The associative memory stores both the address and the content (data) of the memory word. This permits any location in the cache to store any word from the main memory.
In this mapping procedure, the CPU address of 15 bits is divided into two fields. One is index field 9 bits and second is tag equal 6 bits. The number of bits in the index field is equal to the number of address bits required to access the cache memory.
The third type of cache organization called set-associative mapping. In this mapping, each word of cache can store two or more words of memory under the same index address. Each data word is stored together with its tag and the number of tag data items in one word of cache is said to form a set.
The design of the cache depends on 5 factors. These are: