PCI Express System Architecture

PCI Express Architecture:

It is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for PC, Graphics cards, Hard Disk Drives, SSD, Wi-Fi and Ethernet hardware connections, etc.

PCI Express System Architecture

The above figure shows that the PCI Express architecture and the function of the host bridge are to interface the CPU bus with memory and the PCI Express switch. The switch is used to increase the number of PCI’s express ports.

It shows PCI express protocol architecture. The protocol consists of PCI software, transaction, data link, and physical layer. Software Layer The software layer is used for compatibility with PCI, initialization, and enumeration of the devices connected to the PCI express.

PCI Express Physical Layer:

It shows that two devices are connected through a PCI express link (lane); each lane is made of four wires, and each PCI express lane consists of two simplex connections, one for transmitting the packet and another one for receiving the packet. The PCI express lane supports 2.5 Giga transfer/second in each direction.

PCI express link may configure X1, X2, X4, X4, X16, and X32 lanes, where X1 means 1 lane with 4 wires and X4 means 4 lanes with 16 wires and finally, X32 means 32 lanes with 128 wires. PCI-32 means PCI express with 32 lanes. The clock for the PCI express serial link is embedded into the data by using 8B/10B encoding.