ARM Instruction Set Architecture
Advanced RISC Machine (ARM) developed by the Acorn Company. It is a leading supplier of microprocessors in the world, ARM develops the core CPU, and thousands of suppliers add more functional units to the core. It uses two types of instruction called Thumb and Thumb-2. Thumb instructions are 16 bits and thumb- 2 instructions are 32 bits; currently, most ARM processors use 32-bit instructions.
ARM intended for applications that require power-efficient processors, such as telecommunications, data communication (protocol converter), portable instrument, portable computer, and smart card. ARM is a 32-bit RISC processor (32-bit data bus and address bus) with a fast interrupt response for use in real-time
Instruction Decoder and Logic Control: The function of the instruction decoder and logic control is to decode instructions and generate control signals to other parts of a processor for the execution of instructions.
Address Register: To hold a 32-bit address for the address bus
Address Increment: It is used to increment an address by four and place it in the address register.
Register Bank: Register bank contains thirty-one 32-bit registers and 6 status registers.
Barrel Shifter: It is used for fast shift operation.
ALU: 32-bit ALU is used for arithmetic and logic operation.
Write Data Register: The processor put the data in Write Data Register for the write operation.
Read Data Register: When the processor reads from memory it places the result in this register.
ARM Operation Mode:
An ARM can operate in one of the following modes:
1. User mode: Use for normal operation.
2. IRQ mode: This interrupt mode designed for handling interrupt operations.
3. Supervisory mode: Used by the operating system.
4. FIQ mode: Fast interrupt mode.
5. Undefined mode: When an undefined instruction executed.
6. Abort mode: This mode indicates that current memory access cannot be completed, such as when data is not in memory and the processor requires more time to access the disk and transfer a block of data to memory.